Digital charge amplifier and method for converting charge signals into digital signals

ABSTRACT

A circuit for a charge amplifier for converting piezoelectric measurement signals continuously sets the output signal of the amplifier to a value close to zero, such that a reset switch becomes unnecessary. The amplifier includes a pulse generator that provides the output signal of the amplifier in the form of pulses, which are easy to transmit with low interference. The pulse frequency is proportional to the rate of change of charge. The pulses, which are added in a counter, represent a value proportional to the change in the charge since the last counter reset, which is proportional to the present measured value at the measurement element.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to International Application Serial No.PCT/CH2010/000289 filed Nov. 18, 2010, which claims priority to SwissApplication No. CH 1814/09 filed Nov. 25, 2009.

FIELD OF THE INVENTION

The invention relates to a charge amplifier circuit for convertingpositive and negative charge signals Q that are output by apiezoelectric measuring element into a digital signal D which isproportional to the present measured value at the measuring element,comprising a charge amplifier V1 having a charge input and a voltageoutput for converting the detected charge Q into a voltage U2. Theinvention further relates to a method for converting charge signals intodigital signals D.

BACKGROUND

Charge amplifiers are required in particular in connection withpiezoelectric sensors, since these output their measured values in theform of charges. Such sensors detect for example forces, pressures,accelerations, expansions, moments and related physical phenomena. Oncesuch sensors are mounted on movable parts, for example on wheels ofvehicles, the measurement signals are digitalised, in order to be ableto be transmitted to a stator by means of contact-free transmission. Forthis purpose, the determined measurements are typically amplified in acharge amplifier and, by means of analogue-digital converters (A/Dconverters), converted until they are finally transmitted.

As a result of unavoidable interference currents at the amplifier input,which have the same effect as the currents originating from the changesin the charge Q, the amplifier output voltage moves from its originalvalue; it drifts. In order to reduce this interference effect, aresistor is often connected in parallel with the charge amplifier, whichlimits the increase in the output voltage due to drift to an acceptablelevel. The resistor also acts on the measurement signal in a similarmanner, however. The lower cut-off frequency of the charge amplifiertherefore also often increases to values which can no longer betolerated. If the measurement procedure only detects a brief singleevent, this interference effect can be counteracted by activating areset switch shortly before the measurement procedure. In the case oflonger measurement procedures, the choice of the value of resistorfrequently leads to an unsatisfactory compromise between a resultinglower cut-off frequency and the residual drift of the charge amplifier.In addition, in the case of contact-free transmission of the measuredvalue, for example with a moving measurement object, additional effortis necessary to activate the reset switch from of the fixed electronics.

BRIEF SUMMARY OF THE INVENTION

The object of the present invention is to specify a circuit for a chargeamplifier for converting piezoelectric measurement signals, whichreduces the problems mentioned and also supplies a signal without theuse of an analogue/digital converter, which can be easily transmitted bycontact-free means.

The idea of the invention is that the output signal of the amplifier iscontinuously set to a value close to zero, such that a reset switchbecomes unnecessary. In addition, the output signal is provided in theform of pulses, which are easy to transmit with low interference. Thepulse frequency is proportional to the rate of change of charge. Thepulses, which are added in a counter, represent a value proportional tothe change in the charge since the last counter reset, which isproportional to the present measured value at the measurement element.

BRIEF DESCRIPTION OF THE DRAWINGS

Below, the invention is described in more detail by reference to thedrawings. They show:

FIG. 1 a schematic illustration of a circuit according to the invention;

FIG. 2 a circuit for processing a charge signal according to the priorart;

FIG. 3 a schematic illustration of a circuit according to the inventionin an exemplary embodiment with pulsed compensation current;

FIG. 4 a preferred embodiment using diodes;

FIG. 5 a preferred embodiment of a circuit according to the inventionusing transistors;

FIG. 6 a preferred embodiment of a circuit according to the inventionwith constant compensation current.

DESCRIPTION OF EXEMPLARY EMBODIMENTS OF THE INVENTION

FIG. 1 shows a simplified illustration of the functioning of a chargeamplifier circuit according to the invention. The charge Q to bedetected, generated by a piezoelectric measurement element, is appliedat the input of an amplifier V1 with a feedback capacitor C1. As soon asthe amplifier output voltage U2 exceeds or falls below the referencevalue Uref+ or Uref− respectively, the compensation circuit K suppliesdefined compensation charges Qk+ or Qk− via the network R2/C2 to theamplifier input until such time as its output voltage U2 again lieswithin the limits Uref+ and Uref−. With each positive charge unit Qk+ apulse P− is output, and with each negative charge unit Qk− a pulse P+.

These pulses are incremental signals for the charge changes at the inputof V1, or for the input current.

Summing these pulses in an up-/down counter Z produces a measure of thetotal charge previously input and ultimately supplies the desireddigital signal D, which is proportional to the measured value currentlypresent at the measurement element. Preferably, this signal D is avoltage signal.

This circuit is particularly advantageous in the processing of digitalmeasurements and in measurements on moving objects, due to the simplefacility for transmitting the pulses.

A typical circuit for processing a charge signal according to the priorart, as is found for example in piezoelectric measurement technology, isshown in FIG. 2. A piezoelectric measurement element is connected as acharge source Q to the input of an integrating amplifier V1, in thisapplication usually referred to as a charge amplifier. In parallel withthis charge amplifier V1, a capacitor C1 and a reset switch SR areconnected. By closing the reset switch SR the capacitor C1 isdischarged. After this switch is opened, a charge Q applied after thistime reaches the capacitor C1 and induces a voltage at the amplifieroutput, which has the value Q/C1. If a digital signal D is required,then the amplifier output voltage is fed to an analogue/digitalconverter A/D, at the output of which a parallel or serial signal D isthen available.

A resistor R1, which is connected in parallel with the capacitor C1, isintended to limit the increase in the output voltage due to drift to anacceptable level.

FIG. 3 shows an exemplary embodiment of a circuit according to theinvention in simplified form. The components in front of the amplifierV1 represent the parts that are present in every piezoelectricmeasurement device. Q is the charge source, generated by thepiezoelectric measurement element, dQ/dt represents the current flowingdue to changes in Q. Cq is intended to include the total capacitance, Rqthe total leakage resistance of the input circuit, comprising chargesource, cables and amplifier input. Iof is the offset current, Uof thevoltage offset of the amplifier. I1 is the total current flowing fromthe source into the input of the amplifier, comprising the componentsarising from dQ/dt, Iof and Uof/Rq. In an output state of U2=0 an inputcurrent I1 first induces a very small input voltage U1 at the input ofthe amplifier V1 and an output voltage U2, which has the value of theintegral of the current I1 over the time, divided by the capacitance C1.If U2 exceeds the value Uref+0 for negative charge increase at theinput), the comparator amplifier V2 responds and supplies a positiveoutput signal. From the pulse generator G, pulses of exactly definedwidth arrive at the two AND gates &1 and &2. As long as the outputvoltage of V2 is positive, these pulses arrive at the output of the ANDgate &1. They activate the switch S1, which opens the current source Ik+during each pulse duration. Due to this, with every pulse a well-definedcompensation charge Qk+, which is equal to the value of the compensationcurrent source Ik+ multiplied by the pulse duration, arrives at thenetwork R2, C2, C3. This charge Qk reaches the amplifier input andcompensates at least a part of the charge output by the source to V1.When after a sufficient number of compensation charges the input chargeQ is almost completely compensated, U2 again falls below the valueUref+, whereby the following pulses from G can no longer pass throughthe AND gate &1. The pulses output by the AND gate also reach the outputas pulses P. The number of these pulses is equal to the charge that hasflowed to the input divided by the compensation charge Qk and istherefore a measure of the input signal. If Q has the opposite sign(positive charge increase), V3, the AND gate &2, S2 and Ik− start tofunction in an analogous way and induce output pulses P+.

These pulses are incremental signals which are proportional to thecharge changes at the amplifier input. The frequency of the pulses P+ isa measure of the positive charge increase, and likewise the frequency ofthe pulses P− is a measure of the charge decrease.

Of most interest however is usually the integral of the change in chargefrom a particular instant. In this case the pulses are summed in anup-down counter. The pulses P+ and P− pass via a 2-channel transmissionpath Ü to arrive at the two inputs of a counter Z. This counter isinitially set to zero by means of the reset switch R. At the beginningof the measurement process the counter is started by means of the switchS. If the measured value is to be fixed at a particular time, thecounter can be stopped at this time and the signal is preserved in thecounter regardless of drift effects in the amplifier V1. The valuecontained in the counter Z, proportional to the charge Q, can be readout in a known manner as a digital signal D in parallel or serially, andthen further processed.

The source of interference at the amplifier input are due to physicalphenomena and cannot be fully eliminated, since Iof and Uof, whilecertainly small, cannot be reduced to zero and hence the insulationresistance Rq always has a finite value. Even with this improved circuittherefore, genuine static measurements of the charge Q can never in factbe made, and the resistor R2 must have a finite value in order todissipate the interference currents. However, an incremental signalwhich is easily transmitted without interference is present and a resetcircuit on the charge amplifier is not even necessary. Rather, thecounter can be set to zero at any time, easily and quickly.

In the case of abruptly changing signals (large increase in charge in ashort time) the counter is advantageously set to zero in advance andstarted shortly before the expected step change in the signal.

In the case of periodic signals the counter can also be periodically setto zero in an event-driven manner, for example at the beginning of eachperiodic process.

FIG. 6 shows a somewhat differently constructed circuit which hassubstantially the same function as the circuit described in FIG. 3.

It differs from this by the fact that with a positive output voltage ofthe amplifier V2 the switch S1 opens and supplies the compensationcurrent Ik+ via the network R2/C2 to the amplifier input until such timeas U2 again falls below the value Uref. The output voltage of V2 is alsosimultaneously applied to the AND gate &4, which during the time inwhich the compensation current Ik flows, outputs the pulses of the pulsegenerator G as output pulses P− to the output. The number of thesepulses is therefore also proportional to the compensation charge andfinally leads to the delivery of the digital signal D.

For positive changes of charge at the input, essentially the sameapplies to V3, S2 and &3. The switches S1 and S2 only switch thecompensation currents.

From these explanations the following advantages of the invention withrespect to conventional circuit types are evident in particular:

-   -   The measurement signal is directly incremental, and when using a        counter, digital, without an intermediate analogue-digital        converter.    -   A contact-free transmission of the signal is easily possible and        with low levels of interference.    -   The zeroing of the measurement device can be performed on an        external counter; on the charge amplifier itself no switching        operations are necessary.    -   If the counter is stopped, the measurement signal is preserved        for an arbitrary length of time.    -   Due to the fact that the voltage at the amplifier output, and        thus also at the amplifier input, is usually only small, the        effect of the insulation resistance, which is only of finite        size, at the input is reduced.

Function of the Components and Dimensioning Instructions Referring toFIG. 3 and FIG. 6

The frequency of the pulse generator G in the circuit according to FIG.3 is to be chosen high enough so that the maximum expected step chargeat the input is compensated within the time that corresponds to thepermitted delay of the digital signal; the maximum possible frequency isdetermined by the chosen pulse width. In the circuit according to FIG. 6the frequency of the pulse generator G must be high enough to bothobtain a sufficient resolution of the measurement signal and to be ablealso to resolve the short compensation currents, caused by drift effectsand other types of interference, sufficiently well such that noadditional zero point drifts of the counter summing the P+ and P− pulsesoccur.

The reference voltage Uref must have at least the value Qk/C1 forreasons of stability, where Qk stands for the compensation charge unitof the circuit according to FIG. 3, or in the circuit according to FIG.6, essentially the smallest charge delivered at the input in acompensation process, respectively.

Of particular interest is the special case in which R2 is chosen to be alow value, in the extreme case even R2=0 Ohm. Then, the compensationcharges Qk pass directly to the amplifier input. The capacitors C2 andC3 no longer have any effect and can be omitted. The voltage U3 assumesapproximately the value U1 and is therefore negligibly small.

FIG. 4 shows a part of the circuit diagram of FIG. 3, drawn with 4additional components. The switches S1 and S2 are preferably embodied assemiconductor switches. If the leakage currents of these switches areunacceptably large, they can be reduced by high-impedance diodes D1 andD2 inserted in series with the switches. It can be advantageous toforward-bias the diodes by means of the resistors R3 and R4, inparticular if R2 has a high impedance and U3 can then attain valuesdiverging considerably from 0V. These resistors must then have somewhatlower impedance than the diodes, but high enough that the component ofIk flowing through it is negligibly small. In the example shown thiscircuit works as long as U3 does not exceed a value of |11 V|.

EXEMPLARY EMBODIMENT

FIG. 5 shows one of the many possible exemplary embodiments. In thisexample, which represents an implementation of the schematic circuitaccording to FIG. 3, the switches S1 and S2 (of FIG. 3) are integratedinto the current sources. Both AND gates &1 and &2 on the one handoutput the output pulses P+ and P−, and on the other they control thecurrent sources via the transistors T1 to T4. The current sources areformed in a known manner by in each case one amplifier and onetransistor.

The six transistors are shown here without differentiation as FETtransistors, without regard to whether they are junction FETs orMOSFETs.

When the two AND gates &1 and &2 have the output signal 0, thetransistors T1 to T4 are conducting, T5 and T6 are blocked and nocompensation charges are generated.

The generation of a compensation charge Qk+ is described as follows: ifa positive signal is present at both inputs of &1, the output voltage of&1 is different from 0. &1 should be designed such that its outputvoltage is then negative. The self-conducting transistor Ti is therebyblocked and as a result, so is the self-blocking transistor T3. At the+input of the amplifier V4, a voltage formed by the voltage divider R9and R11 is now present. At the resistor R13 therefore, the same voltageis present as at the resistor R9, and the current through this resistoris therefore the desired compensation current. This flows through thetransistor T5; after expiry of the opening time of &1 therefore, thecompensation charge Qk+ has flowed into the network R2, C2, C3.

If both input voltages at &2 are positive, the output voltage of &2 isdifferent from 0. &2 should be designed such that its output voltage isthen positive. At T2, T4, V5 and T6, the generation of the compensationcharge Qk− then occurs in the same manner, but with opposite signs.

The convertible measurement range of a conventional amplifier isinversely proportional to the capacitance of the capacitor C1 that isused. With this charge amplifier according to the invention however, theconversion of a large measurement range is now possible, with only ONEcapacitor C1 being necessary. The switching between different capacitorsC1.1, C1.2, C1.3 . . . of different capacitances in order to be able tocapture different measurement ranges is redundant here, because at alltimes only incremental charges are detected. No special constraints aretherefore placed on this capacitor C1, in particular not on itsinsulation. A loss of charge across C1 is negligible, because thevoltage across C1 only remains for a short time and no amplitudes can bepresent. Therefore, a capacitor C1 with a low capacitance can be chosen.Since capacitors with large capacitances are very voluminous, space isalso saved.

Also, R1 can be completely eliminated.

The use of other components than those used here in the examples, whichlead to the same objective, are considered to be alternative solutionsfrom the inventor's point of view.

LIST OF REFERENCE MARKS

-   Q charge source (e.g. a piezoelectric measurement sensor), or the    charge Q output thereby respectively.-   dQ/dt the current output by the charge source to the amplifier V1.-   Cq Electrical capacitance of charge source, cabling and amplifier    input.-   Rq Insulation resistance of charge source, cabling and amplifier    input,-   Rz Supply cable resistance, possibly artificially increased by    series connection of a fixed resistance to prevent overdriving of    the amplifier V1 in the event of a steep rise in charge, if the    current that can be supplied to C1 by the amplifier output would    otherwise not be sufficient, or if C1 would otherwise have to be    made undesirably large.-   Iof Offset current of the amplifier V1.-   Uoff Offset voltage of the amplifier V1.-   L1 total input current, dQ/dt+Iof+Iof/Rq.-   U1 Input voltage at the amplifier V1.-   V1 high-impedance amplifier.-   C1 Feedback capacitor of the amplifier V1. This can in general be    chosen to be substantially smaller than in the conventional charge    amplifier. It need only be large enough that it can absorb the    charge at the input, not yet compensated by the compensation    circuit, without the amplifier V1 being overdriven.-   U2 Voltage at the amplifier output; due to the compensation circuit    this is repeatedly set to a value <IUref1.-   Uref+/Uref− Reference voltages at which the activity of the    compensation circuit is triggered.-   V2, V3 Amplifiers, which act as comparators for the comparison    between U2 and the reference voltages Uref.-   G Pulse generator, which supplies pulses of defined width and    frequency.-   &1, &2 AND gates, which output a positive output signal when both    inputs have a positive signal. Their outputs activate the switches    S1 and S2.-   &3, &4 AND gates, which in the case of a positive output signal at    V2 or V3 switch the pulses from the pulse generator G through to the    outputs.-   S1, S2 Switches, which switch the compensation currents Ik+ and Ik−;    in the case of FIG. 3 they also switch the pulses from the pulse    generator G through to the outputs.-   Ik+, Ik− well-defined current sources, which each supply an exact    charge Qk+ or Qk− to the network R2, C2, C3 during the period of a    pulse of the pulse generator G.-   R2, C2 are used to transmit the compensation charges to the    amplifier input, R2 must be chosen low enough that the maximum input    error current (Ioff+Uof/Rq) is less than U3 max/R2, since the error    current can only flow away through R2.-   C3 serves to filter the step changes in the compensation charge and    thereby stabilise U3. C3 is advantageously chosen to be less than    C2, in order not to have a large effect on the output signal.-   U3 Voltage across C3; can vary over the whole permitted control    range.-   Ü 2-channel transmission path for the output pulses P+ and P−, by    galvanic, optical, inductive, capacitive or high-frequency means via    transmitter and receiver antenna.-   Z Counter for summing the P+ and P−pulses. The counter is    advantageously designed for outputting positive and negative values.-   D digital counter output, parallel or serial.-   R Reset switch for zeroing the counter.-   S• Starting switch for starting the counting process.-   Qk determines the resolution of the measurement device. If a    resolution in e.g. 1000 steps (1%) is required, and if the    measurement range is being used to the full, then Qk must be at most    1/1000 of the maximum input charge. The values Ik and pulse width of    the pulse generator G are to be chosen accordingly.

The invention claimed is:
 1. Charge amplifier circuit for convertingpositive and negative charge signals Q that are output by apiezoelectric measuring element into a digital signal D that isproportional to the present measured value at the measuring element,comprising a charge amplifier V1 having a charge input and a voltageoutput for converting the detected charge Q into a voltage U2, wherein acompensation circuit K comprising two outputs is connected downstream ofthe voltage output of the charge amplifier V1, wherein the first outputis connected to the charge input of the charge amplifier V1 and thesecond output to a counter Z having two inputs Z+, Z−, and wherein onthe one hand, the compensation circuit K can produce a compensationcharge Qk+ or Qk− respectively, that is proportional to the voltage U2and that can be sent to the charge input of the charge amplifier V1 bymeans of the first output in order to compensate the input signal Q, andwherein on the other hand the compensation circuit can produce a numberof pulses P+, P− that is proportional to the magnitude of eachcompensation charge Qk+ or Qk− produced, and said pulses can be sent toan input Z−, Z+ of the counter Z opposite the sign of the particularcompensation charge Qk+ or Qk− by means of the second output, whereinthe desired digital signal D, which is proportional to the sum of thecharge quanta input beforehand, is available at the output of thecounter Z.
 2. The circuit according to claim 1, wherein the compensationcircuit K comprises a pulse generator G for generating incrementalpulses P, the number of which is proportional to the changes in chargeat the amplifier input.
 3. A charge amplifier circuit for convertingpositive and negative charge signals Q that are output by apiezoelectric measuring element into a digital signal D that isproportional to the present measured value at the measuring element,comprising a charge amplifier V1 having a charge input and a voltageoutput for converting the detected charge Q into a voltage U2, wherein acompensation circuit K comprising two outputs is connected downstream ofthe voltage output of the charge amplifier V1, wherein the first outputis connected to the charge input of the charge amplifier V1 and thesecond output to a counter Z having two inputs Z+, Z−, and wherein onthe one hand, the compensation circuit K can produce a compensationcharge Qk+ or Qk− respectively, that is proportional to the voltage U2and that can be sent to the charge input of the charge amplifier V1 bymeans of the first output in order to compensate the input signal Q, andwherein on the other hand the compensation circuit can produce a numberof pulses P+, P− that is proportional to the magnitude of eachcompensation charge Qk+ or Qk− produced, and said pulses can be sent toan input Z−, Z+ of the counter Z opposite the sign of the particularcompensation charge Qk+ or Qk− by means of the second output, whereinthe desired digital signal D, which is proportional to the sum of thecharge quanta input beforehand, is available at the output of thecounter Z, wherein the compensation circuit K comprises a pulsegenerator G for generating incremental pulses P, the number of which isproportional to the changes in charge at the amplifier input, andwherein two AND gates &1, &2 are connected in parallel downstream of thepulse generator G, said gates also being connected at the input side inparallel with the output of the charge amplifier V1 and each beingconnected at the output side to the input Z− or Z+ of the counterrespectively, wherein depending on the sign of U2, the pulses passthrough the gate &1 or &2 and can be detected in the counter Z at Z− orZ+.
 4. The circuit according to claim 3, wherein two compensationamplifiers V2, V3, which are connected in parallel between the output ofthe charge amplifier V1 and the AND gates &1 or &2 respectively.
 5. Thecircuit according to claim 4, wherein two current sources Ik+, Ik− forgenerating the compensation charges Qk+ and Qk−.
 6. The circuitaccording to claim 5, wherein two switches S1, S2 each downstream of oneoutput of the current sources Ik+, Ik−, which are also each connected atthe input side to one of the outputs of the AND gates &1, &2, whereinthe switches S1, S2 can send current from the current sources Ik+, Ik−to the charge input of the charge amplifier V1 during a pulse duration.7. The circuit according to claim 6, wherein diodes DI, D2, which areconnected downstream to one each of the switches S1, S2 in series. 8.The circuit according to claim 5, wherein two switches S1, S2 downstreamof one output each of the current sources Ik+, Ik−, which at the inputside are also each connected to one of the outputs of the compensationamplifier V2 and V3, to allow a current to pass from the current sourceIk+ in the case of a positive output voltage of the compensationamplifier V2, or from the current source Ik− in the case of a negativeoutput voltage of the compensation amplifier V3.
 9. The circuitaccording to claim 8, wherein transistors or mechanical switches areused as switches, at least in part.
 10. The circuit according to claim1, wherein the counter comprises a reset switch R for resetting thecounter to zero and/or a start switch S for starting the countingprocess.
 11. The circuit according to claim 1, further comprising meansto enable the counter pulses to be transmitted unmodulated or modulatedonto a carrier, galvanically or by inductive or capacitive or opticalcouplers or transmitter and receiver antennas, to the counter.
 12. Thecircuit according to claim 1, wherein the digital signal D is a voltagesignal.
 13. Method for converting positive and negative charge signals Qthat are output by a piezoelectric measuring element into a digitalsignal D that is proportional to the present measured value at themeasuring element, comprising the steps that: a charge amplifier V1converts the input charge signal Q into an analogue voltage signal U2,the voltage signal U2 is passed into a compensation circuit K downstreamof the charge amplifier V1, on the one hand the compensation circuit Kproduces a compensation charge Qk+ or Qk− respectively that isproportional to the voltage U2 and, to compensate the input signal Q,sends it to the charge input of the charge amplifier V1 by means of afirst output, and that on the other hand the compensation circuit Kproduces a number of pulses P+, P− that is proportional to the magnitudeof each compensation charge Qk+ or Qk− produced and sends them to aninput Z−, Z+ of the counter Z opposite the sign of the particularcompensation charge Qk+ or Qk− by means of the second output, and saidcounter sums the pulses and delivers the respective sum as the desireddigital signal D.